Terms and Conditions

Hardware IPs

Cost structure for end users:

There is a base price per usage (design). This base price includes:

• Full design kit:
   - VHDL/Verilog synthesis (time limited)
   - VHDL/Verilog simulation model
   - VHDL/Verilog verification suite
   - documentation, application note
   
• No additional license fees for quantities up to 5,000 pieces.

Additional volume fees for quantities greater 5,000 pieces:
0.001 % of base price per chip.

Discounts

- Multiple usage of same customer and same core
- Fraunhofer IIS as design center or ASIC provider

Please ask for details.
 

Audio Software IPs

In general, the software IPs offered for the audio platform are available for a fixed price per project (design).

The base price includes:

• The core audio decoder as precompiled object code
• Framework configuration / adaptation layer and sample IO drivers as source code
• Documentation for the software and interfaces
• List of recommended and required hardware extensions of the ARC processor

As for all MP3 or AAC software, additional licenses for the usage of certain patents and/or for production may be required. Please visit www.mp3licensing.com for details on MP3 licensing. For AAC, please contact Fraunhofer IIS - Audio and Multimedia Realtime Systems.