FHG_VITERBI: FAQs

• Has the FHG_VITERBI additional features like BER measurement, synchronisation or punctioring?
   
  There are no additional features like BER measurements, synchronisation or punctioring. This can be done by additional logic built around the decoder core. We can offer to support you in this task.
   
• Is it possible to configure the FHG_VITERBI in circuit?
   
  As you may have seen in the documentation, the decoder is parametrized pre synthesis. After mapping to a dedicated ASIC/FPGA technology the parameters are fixed and the design is optimized for one set of parameters. If you need only different data formats or punctioring, this can be done in front of the decoder. But if you need to configure the polynomial or datarate in circuit, our decoder cannot support this features.
   
• What is the estimated gatecount for FHG_VITERBI_PAR?
   
  We have made some estimations based on K=7, Code Rate R=1/2, 3 soft bits.
  The estimated gate count for the parallel Viterbi decoder architecture FHG_VITERBI_PAR dependent on the survivor length H:
  H=35: 51,000 gates
  H=40: 54,000 gates
  H=45: 57,000 gates