FHG_VITERBI

Purpose

The library FHG_VITERBI provides four different parameterizable and synthesizable Viterbi Decoder architectures for convolutional code rates Rc = 1/n.
Each architecture is suitable for a certain range of symbol rates. For all Viterbi decoder architectures common parameters are the generator polynomials, the code rate, the wordlength of the soft-input words and the survivor length.

Features

• Viterbi Decoder Architectures
  - FHG_VITERBI_PAR:
    parallel architecture for high data rates
  - FHG_VITERBI_SER:
    serial architecture for low-rate, low-complexity applications
  - FHG_VITERBI_PIPE:
    serial-pipelined architecture
  - FHG_VITERBI_SP:
    parameterizable serial-parallel architecture, trade-off data rate
    vs. chip area possible
   
• Fully synthesizable
   
• Technology independent (FPGA and ASIC)
   
• Parameters
  - Code rate (Rc = 1/n)
  - Constraint Length
  - Generator Polynomials
  - Survivor Length of Viterbi algorithm
  - Wordlength of Soft-Input Words
  - Number of ACS Calculators (FHG_VITERBI_SP only)
  

Documentation

For download:

FHG_VITERBI documentation (Adobe® Acrobat v3.0 PDF file) 170 kB

If you don't have Adobe® Acrobat Reader you can download it.

Design Kit

• Technology Independent Implementation as Synopsys Design Ware Components
• VHDL/Verilog Source Code Simulation Models
• Auxiliary Simulation Models for User Testbenches
• Synthesis and Testsynthesis Scripts

Design Support, Netlist Synthesis Service and Consulting available.

Requirements

• Simulation
  • VHDL IEEE-1076 Simulator
  • Verilog IEEE-1364 Simulator
• Synthesis
  • Synopsys Design Compiler

References

For more detailed information on the theory of the FHG_VITERBI library please refer to standard literature about the Viterbi algorithm and Viterbi decoders (e.g. Viterbi & Omura: Principles of Digital Communication and Coding, McGraw-Hill, 1985).

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