FHG_USBSIM

Universal Serial Bus Simulation Environment

Purpose

The USB simulation environment provides the ability to simulate and verify USB host, hub and function cores at a functional level using easy programmable simulation models for USB host/hub/function.
 
These simulation models are provided precompiled. Every simulation model may be independently configured using generic parameters during its instantiation. The simulation environment contains a Virtual Analyzer module which can be used to monitor the USB data lines and to verify the USB traffic in a comfortable way.

Features Simulation Environment

The USB Simulation Environment consists of the following components:

• USB Host Model
• USB Function Model
• USB Hub Model
• Virtual Analyzer with Java-GUI
• Examples of test cases

USB Host Model

The USB Host model can be used to simulate transactions initiated by the USB Host to test the correct behaviour of an USB device. It can be controlled by a special control file.

The key features of the USB Host model are:

• Generates USB low level protocol, sends and receives USB data stream
• Supports all transfer types (control, interrupt, bulk, isochronous)
• Generates/detects static bus events like Suspend/Resume/USB Reset
• Supports Full speed and mixed Full/Low speed transaction generation
• Automatically detects/generates USB handshake with timeout detection
• Supports OHCI/UHCI framework behaviour
• Controllable by text file at USB high level protocol information
• Optional debug output
• Support generation of packets with CRC- or bit stuff errors

USB Function Model

The USB Function Model is used to simulate the behaviour of a USB Function. It supports Endpoint 0 for Device Requests. The following standard requests are supported by the function model:

• GetDescriptor (Device, Configuration)
• SetAddress
• SetConfiguration

A special request (SetError) enables/disables various error conditions like:

• Data overrun
• Bitstuff error
• CRC error
• Stall error
• Timeout error

The Function Model can operate in full speed mode or in low speed mode. Additional features are a free configurable loop back endpoint and the support of isochronous transfers.

USB Hub Model

The USB Hub Model can be used to connect additional USB Functions to a USB Host. The number of downstream ports can be configured using a generic parameter.

The hub transports downstream traffic from the upstream port to USB functions in broadcast mode. Data from a function will be transported to the upstream port.

The hub simulation model is able to detect low speed PRE-tokens. If a PRE-token is detected, all ports connected to low speed USB functions are enabled, otherwise these ports are disabled to prevent low speed devices from full speed traffic.

Virtual Analyzer

The Virtual USB Analyzer allows the tracing of all signals at the USB data lines and an easy evaluation using a special Java application. A VHDL component is instantiated in the used test bench which generates a pattern file with all traced values at the data lines. The Virtual Analyzer module has its own dpll for clock recovery.

The basic features of the Virtual Analyzer are:

• Traces USB data lines and generates pattern file
• Own clock recovery
• Java application for evaluation of pattern file
• Generation of abstract text file representing the transaction layer

Documentation

Please ask for details.

Design Kit

• VHDL precompiled simulation models
• Other tool support on request

Design Support, Netlist Synthesis Service and Consulting available.

Requirements

• Simulation
  • VHDL IEEE-1076 Simulator
  • Verilog IEEE-1364 Simulator
• JAVA GUI
  • JDK v1.2 or later (Java 2 Std Development Kit) or
  • JRE v1.2 or later (Java Runtime Environment)

Terms & Conditions

Details