FHG_USB2

Universal Serial Bus 2.0 Function IP

Purpose

The FHG_USB2 is an USB function core with an 16/32-bit microprocessor interface. It is fully compliant with USB 2.0 specification and supports high-speed mode with a data rate of 480 MBit/s and full-speed mode with 12 MBit/s. Its parameter set enables the designer to enhance the USB interface and to tailor it to the applications needs.

Features

• Synthesizable USB function core compliant to USB 2.0 specification
• High- and full-speed capable
• Configurable for 16 or 32 bit data interface
• UTMI compliant interface (USB Transceiver Macrocell Interface)
• Dual port RAM interface
• Scalable number of endpoints (max. 15 IN / 15 OUT plus bi-directional control endpoint 0)
• Supports large buffer management
• High Speed Data Channel (HSDC) interface for high speed/low cost applications
• Suspend/Resume/Remote Wakeup support
• Technology independent (FPGA and ASIC)

Documentation

Please ask for details.

Design Kit

• Technology independent implementation as Synopsys Design Ware component
• VHDL precompiled simulation models
• VHDL/Verilog USB 2.0 compliance test suite
• Synthesis scripts
• Other tool support on request

Design Support, Netlist Synthesis Service and Consulting available.

Requirements

• Simulation
  • VHDL IEEE-1076 Simulator
  • Verilog IEEE-1364 Simulator, netlist only
• Synthesis
  • Synopsys Design Compiler

Terms & Conditions

Details