FHG_RS_DEC

FHG Reed-Solomon Decoder

Purpose

The FHG_RS_DEC is a parameterizable and synthesizable Reed-Solomon decoder. Its parameter set enables the designer to implement Reed-Solomon decoders for any codeword length and any error correcting capability, and thus provides versatility for the design of corresponding applications. The Reed-Solomon decoder uses (N, K) Reed-Solomon codes for block error correction, being the number of correctable symbol errors within one block:
t = (N-K)/2.

Features

• Fully parameterizable Reed-Solomon decoder
• Fully synthesizable
• Codeword length and error correcting capability parameterized
• Generator polynomial parameterized
• Registered inputs and outputs
• Technology independent (FPGA and ASIC)

Documentation

For download:

FHG_RS_DEC documentation (Adobe® Acrobat v3.0 PDF file) 60 kB

If you don't have Adobe® Acrobat Reader you can download it.

Design Kit

• Technology Independent Implementation as Synopsys Design Ware Components
• VHDL/Verilog Simulation Models
• Test Suite
• Synthesis and Testsynthesis Scripts

Design Support, Netlist Synthesis Service and Consulting available.

Requirements

• Simulation
  • VHDL IEEE-1076 Simulator
  • Verilog IEEE-1364 Simulator, netlist only
• Synthesis
  • Synopsys Design Compiler

References

For more detailed information about the FHG_RS_DEC refer to standard literature about the Reed-Solomon decoding procedure and Reed-Solomon decoders (e.g. Richard E. Blahut: "Theory and Practice of Error Control Codes", Addison-Wesley, 1983).

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