FHG_RAMBIST

Purpose

The FHG_RAMBIST is a RAM architecture and technology independent Built In Self Test Controller for Random Access Memories (RAM). Its parameter set enables the designer to tailor the RAM BIST to the applications needs.

Features

• Fully static, synthesizable RAM BIST
• Independent Set of Test Algorithms for Application specific Test Coverage
• RAM Structure independent Algorithms
• Data Retention Rest
• Single Port (1RW) and Dual Port (1R1W, 2RW) Implementations
• Master Slave, simultaneous multiple RAM Test
• Optional transparent Bypass Mode (hidden RAM test during scan test)
• Optional Write Through Test Mode
• Optional Zero Output
• BIST Logic Scan testable
• JTAG controllable
• Technology independent (FPGA and ASIC)

Documentation

Please ask for details.

Design Kit

• Technology Independent Implementation as Synopsys Design Ware Components
• VHDL/Verilog Simulation Models
• VHDL/Verilog Compliance Test Suite
• Synthesis and Testsynthesis Scripts

Design Support, Netlist Synthesis Service and Consulting available.

Requirements

• Simulation
  • VHDL IEEE-1076 Simulator
  • Verilog IEEE-1364 Simulator
• Synthesis
  • Synopsys Design Compiler

Terms & Conditions

Details