FHG_I2C

Purpose

The I2C-bus interface serves as a bidirectional on-chip communication interface between parallel-bus applications and the I2C-bus. The interface implements the I2C-bus protocol for master and slave applications. Its functional parameterization allows an application-specific implementation without hardware overhead.

Features

• Parallel interface to master and slave applications with handshaking
• Parameterizable functionality (master/slave receiver/transmitter)
• Parameterizable address mode (7/10 bit)
• Parameterizable transfer rate (100-400 kbit/s)
• Separate ports for each functional block
• No data storage, which ensures uncorrupted data in case of transfer errors
• Technology independent (FPGA and ASIC)
• Silicon proven

Documentation

To download the documentation, please choose the short or large version:
Short FHG_I2C Documentation (Adobe® Acrobat v3.0 PDF file) 44 kB
Large FHG_I2C Documentation (Adobe® Acrobat v3.0 PDF file) 132 kB

If you don't have an Adobe® Acrobat Reader you can download it.

Design Kit

• Technology Independent Implementation as Synopsys Design Ware Component
• VHDL/Verilog Source Code Simulation Models
• HDL/Verilog I2C Compliance Test Suite
• Auxiliary Simulation Models for User Testbenches
• Synthesis and Testsynthesis Scripts
• Example Design and Testchip available

Design Support, Netlist Synthesis Service and Consulting available.

Requirements

• Simulation
  • VHDL IEEE-1076 Simulator
  • Verilog IEEE-1364 Simulator
• Synthesis
  • Synopsys Design Compiler

References

Philips Semiconductors: The I2C-bus and how to use it (including specifications), April 1995.

Terms & Conditions

Details