FHG_DRM Base Band IP

Purpose

The CorePool component FHG_DRM offers a “pure-hardware” solution for Digital Radio Mondiale (DRM) base band decoding. The FHG_DRM IP is based on an proprietary signal processing architecture. This enabled a scalable implementation with a small footprint and minimal dependency on third party IP or specific silicon vendors or manufacturing technologies.

The CorePool FHG_DRM base band IP may be combined with service demultiplexing and audio decoding (AAC/SBR, HVXC, CELP) software libraries running on an embedded ARM9 core or any other suitable host processor. The combination of both IPs, together with an analog tuner front end based on COTS components offers an extremely competitive low cost and low power DRM receiver implementation for the mass market.

Features

• Implements the complete DRM base band processing, including signal acquisition and tracking, signal conditioning, viterbi and multi-level decoding.
• Interfaces to standard (analog) tuner frond ends and outputs digital bit stream (DRM service multiplex, MDI) to service/audio decoder.
• Fully synthesize-able, independent of any specific semiconductor manufacturer or process.
• Free of third-party intellectual property cores (e.g. CPU cores), no hardware related third-party IPR licensing issues or royalties.
• Minimal size (compared to DSP based base band solutions)
• flexible, arbitrary data bit-widths (minimized logic)
• enables clock/power vs. chip area trade-offs
• inherent parallelism, scales easily (e.g. for 2-arm diversity receiver)
• Available in different configurations and with different interface options, including interface option for I2C or for industry standard AMBA bus.
• Technology independent (FPGA and ASIC)

Documentation

For download: FHG_DRM Data Sheet Summary (Adobe® Acrobat v4.0 PDF file) 201 kB

If you don't have Adobe® Acrobat Reader you can download it.

The full data sheet is available under NDA.

Design Kit

• Technology Independent Implementation as Synopsys Design Ware Component
• Auxiliary Simulation Models for User Testbenches
• Synthesis and Testsynthesis Scripts

Design Support (Hardware and Software) and System Integration available.

Requirements

• Simulation
• VHDL IEEE-1076 Simulator
• Verilog IEEE-1364 Simulator
• Synthesis
• Synopsys Design Compiler (recommended)

References

For more details about DRM, please visit to following sites:

• Fraunhofer IIS – DRM contributions and products
• Digital Radio Mondiale (DRM) Home Page
• DRM Standard at ETSI direct DRM standard download (requires ETSI account or registration)

Terms & Conditions

We offer special licensing conditions for this IP. Please ask for details