FHG8051 Microcontroller
Purpose
The FHG8051 is a high performance, opcode compatible core version of
the industry standard 8051 microcontroller for ASIC and FPGA implementations.
Its parameter set enables the designer to enhance the CPU performance and
to tailor the architecture to the applications needs.
Features
- 8-Bit Synthesizable Microcontroller Core
- Opcode and Cycle Equivalent to Industry Standard 8051
- Fully Static, Microcode Free Design
- Up to 64K Bytes Program Memory Address Space
- Up to 64K Bytes Data Memory Address Space
- Up to 256 Bytes Internal Data Memory
- Up to 128 Special Function Registers (SFR)
- Idle, Power Down Mode
- Programmable Clock and Wait State Generator
- Technology independent (FPGA and ASIC)
- Silicon proven
- Optional 7 Interrupt Sources in 2 Priority Levels or no Interrupt Unit
- Optional True 8051 Cycle Operation or Reduced Cycle Mode for Enhanced Performance
- Optional PCON, P1, P3 or Second DTPR Register
- Optional Area Reducing NOP Behaviour for MUL, DIV or DA Opcodes
- Optional Program Memory Write Mode
Documentation
To download the documentation, please choose the short or large version:
Short FHG8051
Documentation (Adobe® Acrobat v3.0 PDF file) 32 kB
Large FHG8051
Documentation (Adobe® Acrobat v3.0 PDF file) 130 kB
If you don't have an Adobe® Acrobat Reader you
can download it.
Design Kit
- Technology Independent Implementation as Synopsys Design Ware Component
- VHDL/Verilog Source Code Simulation Models
- VHDL/Verilog 8051 Compliance Test Suite
- Auxiliary Simulation Models for User Testbenches
- Synthesis and Testsynthesis Scripts
- Example Design and Testchip available
FREE: Please send
me the Design Kit.
Design Support, Netlist Synthesis Service and Consulting available.
Requirements
- Simulation
- VHDL IEEE-1076 Simulator
- Verilog IEEE-1364 Simulator
- Synthesis
Terms & Conditions
Details
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